1. Field of the Invention
The present invention relates to a semiconductor device, and to a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device structured to accommodate a high density of integrated circuit chips, and a technique for stacking these chips.
2. Description of Related Art
Memory (DRAM) packaging is entering a transition from TSOP to ball grid array at the single chip level. Since the 1970's, high-end server users of DRAMs have doubled their memory density by piggyback stacking of single chip devices. With the advent of area array footprints for DRAM, piggyback stacking is more difficult. Where peripheral lead frame packages lend themselves to piggyback stacking, Ball Grid Array's (BGAs) do not. DRAM memory chip packaging differs from other wirebonded devices in that addressing pads are positioned in the center of the chip rather than at its periphery. To stack area array modules, one or more wiring layers must be added between the vertical decks of the stack to fan signals out to the periphery of the lower device, then back into the BGA beneath it. This adds cost for additional substrates, as well as increased impedance, electrical noise, and time-of-flight delays to the circuit paths due to the additional wiring.
Vertical stacking of memory chips and packages has been the traditional method for doubling memory density on a given surface area. Electrical connections peripheral to the chip are used for common signals between the upper and lower devices. With decreasing memory access times, the impedance effects of memory packaging are becoming technology driven limitations. Generally, two or more memory chips are stacked one on another, while keeping their directions or orientations the same. The bonding pads of one memory chip are disposed in proximity to the bonding pads of the other memory chip. The upper memory chip is stacked over the lower memory chip.
For peripheral lead packaging of chips with center bond buses, packaging must include circuit traces to fan signals to the periphery. When using area array packaging of chips with center bond busses, stacking requires increasing the upper device trace length to fan out signals from the center to the periphery, and then back to the lower device. For example, in center bond bus DRAM in FBGA, center stacking of one chip to another causes signals from the top chip to travel a much greater distance traversing around the lower chip in order to escape the stack. Complex wiring structures having multiple solder interconnects are used to accomplish the wiring of this signal circuitry in the prior art. The resultant wiring generally exhibits higher impedance and degraded reliability than a non-stacked version.
FIGS. 1A–1C depict examples of the prior art stacking of chips having bus wiring at the edge of the chip and with center bond busses. Stacked integrated circuit chips 10 and 12 are shown with bus wiring 14, 16 attached to the substrate 18. In FIG. 1A, IC chips 10, 12 are stacked, one on top of another, with the bus wiring traversing in parallel directions to the substrate. In FIG. 1B, two chips 20, 22 with center busses 24, 26 are shown in a stacked configuration. Connecting the top IC 22 requires extending the bus wires 26 over the chips to the substrate 28 below. Connections for the bottom IC 20 may be made directly down onto the substrate top surface (not shown), or through a gap 29 in the substrate, with attachment to the substrate bottom surface or an inner layer therein. In another embodiment, shown in FIG. 1C, chips 30, 32 with center bus bonds 34, 36 are stacked over substrate 40 and attached by adhesive cement 38 therebetween. Again, connections require extension of the bus wires over each chip to the substrate.
In U.S. Patent Publication No. 2002/0180060, published on Dec. 5, 2002 and issued to Masuda, et al., entitled “SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME,” memory chips are mounted over a base substrate with one of them being overlapped with the upper portion of the other. They are stacked with their faces turned in the same direction. The bonding pads of one of the memory chips are disposed in the vicinity of the bonding pads of the other memory chip. Importantly, Masuda teaches offsetting the second semiconductor chip in a direction parallel to the first semiconductor chip and in a direction perpendicular to the first chip, such that the bus wires at the edge of each chip are offset when connected to the substrate. This facilitates visual inspection of the bus wire connections.
In International PCT Application No. WO 01/80317 issued to Helder on Oct. 25, 2001, entitled “SEMICONDUCTOR COMPONENT COMPRISING SEVERAL SEMICONDUCTOR CHIPS,” semiconductor chips of a chip stack are arranged in an offset manner in relation to one another. Each chip is then connected to the series of conductors of the carrier substrate by electric connections. Importantly, Helder does not teach using chips having a center bus, nor are attachment schemes for center bus bonds disclosed.
The present invention avoids the added increase in trace length for connections from the upper device in the stack. Packaging is simplified in that long, multiple interconnects for escape of signals from the upper device are avoided. This configuration reduces cost while simultaneously increasing reliability. Electrical impedance, noise, and signal time of flight characteristics for the upper device are improved.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus and method for promoting size and thickness reduction through the stacking of integrated circuit memory chips.
It is another object of the present invention to provide an apparatus and method for stacking chips having center bus bonds.
A further object of the invention is to provide an apparatus and method for reducing the manufacturing cost of a semiconductor device having a plurality of semiconductor chips stacked on one another.
It is yet another object of the present invention to provide an apparatus and method for decreasing memory access times and impedance effects through semiconductor topology.
An additional object of the invention is to provide a method for assembling offset stacked chips onto a memory module such that module memory density is nearly doubled, while retaining the advantages of offset stacked devices.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.